3D (three dimensional) integrated circuits have become very popular in recent years due to the increased levels of integration they provide. 3D integrated circuits utilize through silicon via (TSV) structures which are via openings that extend completely through a semiconductor substrate and enable devices above and below the substrate to be coupled to one another and to devices internal to the substrate and provide the interconnects compatible with 3D wafer level packaging. When filled, the TSV structures may serve as signal lines or other purposes. Signal lines can carry and create significant amounts of electrical noise that adversely affects semiconductor devices such as active transistors, in their vicinity.
It would therefore be desirable to take advantage of the advanced integration levels afforded by 3D integrated circuits using TSV structures while avoiding problems associated with electrical noise created by such TSV structures.